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References
Glossary
Below is a glossary of helpful terms to bring you up to speed on Altera devices.
Term
Adaptive logic module (ALM)
Configuration via Protocol (CvP)
Embedded HardCopy Blocks
Equivalent LE
Fractional phase-locked loops
(Fractional PLL)
Global clock networks
Hard processor system (HPS)
Logic element (LE)
Macrocells
Memory logic array blocks (MLABs)
On-chip termination (OCT)
Periphery clocks (PCLKs)
Plug & Play Signal Integrity
Programmable Power Technology
Real-time in-system
programming (ISP)
Regional clocks
System on a chip (SoC)
Variable-precision blocks
Definition
Logic building block, used by some Altera devices, which provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided
between two combinational adaptive LUTs (ALUTs).
CvP is a configuration method that enables you to configure the FPGA using industry-standard protocols.
Currently CvP supports the PCIe protocol.
These metal-programmable hard IP blocks deliver up to 14M ASIC gates or up to 700K additional LEs to
harden standard or logic-intensive applications.
Device density represented as a comparable amount of LEs, which uses the 4-input LUT as a basis.
A phase-locked loop (PLL) in the core fabric, fractional PLLs provide increased flexibility as an additional
clocking source for the transceiver, replacing external VCXOs.
Global clocks can drive throughout the entire device, serving as low-skew clock sources for functional
blocks such as ALMs, DSP blocks, TriMatrix memory blocks, and PLLs. See regional clocks and periphery
clocks for more clock network information.
This processor system is a hardened component within the SoC, which comprises a dual-core
ARM Cortex-A9 MPCore processor, a rich set of peripherals, and multiport memory controllers.
This logic building block, used by some Altera devices, includes a 4-input LUT, a programmable register,
and a carry chain connection. See device handbooks for more information.
Similar to LEs, this is the measure of density in MAX series CPLDs.
MLABs are dual-purpose blocks, configurable as regular logic array blocks or as memory blocks.
Support for driver impedance matching and series termination, which eliminates the need for external
resistors, improves signal integrity, and simplifies board design. On-chip series, parallel, and differential
termination resistors are configurable via Quartus II software.
PCLKs are a collection of individual clock networks driven from the periphery of the device. PCLKs can be
used instead of general-purpose routing to drive signals into and out of the device.
This capability, consisting of Altera’s adaptive dispersion engine and hot socketing, lets you change
the position of backplane cards on the fly, without having to manually configure your backplane
equalization settings.
This feature automatically optimizes logic, DSP, and memory blocks for the lowest power at the required
performance. Only the blocks with critical-path logic need to be in high-performance mode; all others are
in low-power mode.
This capability allows you to program a MAX II device while the device is still in operation. The new design
only replaces the existing design when there is a power cycle to the device, so can perform in-field updates
to the MAX II device at any time without affecting the operation of the whole system.
Regional clocks are device quadrant-oriented and provide the lowest clock delay and skew for logic
contained within a single device quadrant.
An SoC is an embedded system that consists of a processor, peripherals, and custom hardware integrated
on a single device.
These integrated blocks provide native support for signal processing of varying precisions—for example,
9x9, 27x27, and 18x36—in a sum or independent mode.
Altera Product Catalog
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2013
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www.altera.com
87
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相关PDF资料
DK-K7-CONN-CES-G KINTEX-7 FPGA CONNECTIVITY KIT
DK-K7-EMBD-CES-G-J KINTEX-7 FPGA EMBEDDED KIT JAPAN
DK-MAXII-1270N KIT DEV MAXII W/EPM 1270N
DK-N2EVAL-3C25N KIT DEV NIOS II CYCLONE III ED.
DK-NIOS-2C35N NIOS II KIT W/CYCLONE II EP2C35N
DK-NIOS-2S60N NIOS II KIT W/STRATIX II EP2S60N
DK-PCI-2C35N PCI KIT W/CYCLONE II EP2C35N
DK-PCIE-2SGX90N PCIE KIT W/S II GX EP2SGX90N
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